A conditional clock overlap for the diamond prefix.
A proved local preparation box reduces the controller sensitivity enough to admit a fast SAR and LC component route mathematically.
The preparation gives a tighter region to prove.
Near the specified CD-1 initial state, lifted angles stay within 1/100; electric and imaginary matter coordinates within 1/50; real matter coordinates lie between 2/3 and 3/4. Exact Hamiltonian majorants give target Lipschitz bound 4, actual speed bound 8/5 and Gauss bound 4.
A joint state/reconstruction and actuator-tracking barrier keeps nominal and both fault laws within this box through the short decision window. This is a proof on the specified prefix, not a sampled-trajectory assumption or a full-horizon replacement.
The physical clock interval is nonempty.
| Proposed quantity | Conditional requirement |
|---|---|
| Clock interval | 8/575 < t₀ ≤ 1/48 seconds |
| Example physical clock | t₀=1/60 second |
| Command period; additional true latency | 1 μs; at most 2 μs |
| Identified actuator time constant | At most 1 μs |
| Input error; complete command error | 3/100000; 1/25000 |
| Total residual; slack below 1/100 | 481/50000=0.00962; 19/50000 |
The plant model now retains series resistance and actively cancels it. The operating-band premises are L≥0.85 H, C≥0.8 mF and R≤6.6125 Ω on every canonical pair. Under balanced common-action scales these imply λ<48t₀. Actual component calibration must substantiate those premises.
A specific component route can now be screened.
The candidate route uses Hammond 193S chokes, Nichicon UES1C102MHM bipolar capacitors, AD4630-24 acquisition and AD5791 command converters. Manufacturer sources and exact conditions are linked in the manuscript and machine-readable record.
Acquisition is proposed at 2 MSPS; commands update at 1 MHz. The DAC serial frame does not fit fresh 2 MHz writes. A complete parallel transfer, evaluation and command-latching design must close the proposed latency. Independent coupling, actuator and work readout remain required.
The two fault-detection slacks improve to about 0.00624634 and 0.00704346. A ten-time-constant preload bounds release tracking by 33/40000, provided the specified hold-history and distortion premises hold.
Clock overlap is not hardware admission.
The capacitor’s published rated-voltage leakage limit does not certify the much smaller current-residual allowance at the proposed test voltage. Measure the actual charge/voltage relation, leakage or bounded compensation, ESR and dielectric memory. Measure the choke’s flux/current law and hysteresis at operating bias.
A conditional noise-family bound is supplied for at most 10000 controller-coordinate errors, given explicit sub-Gaussian tails. Supplier RMS or SNR does not establish that premise. Calibration, witnesses, endpoints and clocks need separate joint uncertainty allocation.
The next return must close operating-band plant identification, full timing, input and command errors, actuator response, startup and independent sensing. No purchases or experiments have occurred. Hardware remains HOLD; no full CD-1 campaign or SDW admission is asserted.
Read the earlier clock–plant compatibility theorem →